1. Technical Field
Power-up signal generators for semiconductor memory devices are disclosed and, more particularly, to a power-up signal generator is disclosed for generating a power-up signal that is disabled during a deep power down entry and enabled by an internal power supply voltage during a deep power down exit.
2. Background of the Related Art
A deep power down entry designates a state in which all internal power supply voltages used inside a dynamic random access memory (DRAM) device are turned off to reduce a standby current drain when the DRAM device is not used for a period time. A power-up signal is a signal indicating that a DRAM device is able to operate normally. When the power-up signal is enabled at a high level, the DRAM device operates normally.
FIGS. 1 and 2 are circuit diagrams of power-up signal generators known in the prior art. The power-up signal generator includes a voltage divider 11 for dividing an external power supply voltage Vext, a pull-up unit 12 for pulling-up a divided voltage A, a driving unit 16 for receiving the divided voltage A to generate a power-up detection signal DET for determining the time that a power-up signal PWRUP is enabled, and a driving unit 15 for receiving the power-up detection signal DET to generate the power-up signal PWRUP. The driving unit 16 includes a pull-up unit 14 for pulling-up the power-up detection signal DET and a pull-down unit 13 for pulling-down the power-up detection signal DET.
The voltage divider 11 includes resistors R1 and R2 connected in series between the external power supply voltage Vext and a ground voltage Vss. The pull-up unit 12 includes a NMOS transistor N1 that is connected between the external power supply voltage Vext and a node SN1 and the divided voltage A is applied to its gate. The pull-down unit 13 includes an NMOS transistor N2 connected between an output node SN2 and the ground voltage Vss. The divided voltage A is applied to a gate of the NMOS transistor N2. The pull-up unit 14 includes a resistor R3 connected between the external power supply voltage Vext and the output node SN2. The driving unit 15 includes an inverter IV1 connected between the external power supply voltage Vext and the ground voltage Vss. The inverter IV1 inverts the power-up detection signal DET to output the power-up signal PWRUP.
The construction of the power-up signal generator of FIG. 2 is the same as that of the power-up signal generator of FIG. 1, except that a PMOS transistor P1 is used in the pull-up unit 14 instead of the resistor R3. Accordingly, a detailed description of FIG. 2 is omitted.
In the prior power-up signal generator, the power-up signal PWRUP is disabled at a low level until an internal power supply voltage, which is generated from the external power supply voltage Vext, reaches a stable level. The power-up signal PWRUP is enabled at a high level when the current flowing through the resistor R3 (FIG. 3) or the PMOS transistor P1 (FIG. 2) is larger than the current flowing through the NMOS transistor N2.
The power-up signal PWRUP is always enabled in a deep power down entry, as well as in a deep power down exit. The power-up signal PWRUP is always enabled because some semiconductor elements such as a clock buffer, or a mode register set, etc., should be in an operation state during the deep power down exit.
However, if the power-up signal PWRUP is enabled at a high level in a deep power down entry, the DRAM device operates in the state in which the internal power supply voltage is not generated. Accordingly, the semiconductor elements that operate by the internal power supply voltage will malfunction because the internal power supply voltage Vint is not provided thereto.